Microprocessors typically perform operations on 1 bit, 8 bits (1 byte), 16 bits, 32 bits or 64 bits of data. Therefore, microprocessor systems may be designed to allow access to memory in blocks that are also 1, 8, 16, 32, or 64 bits wide.
However, some types of data have a different width. For example, a stream of physical measurements (input) or a stream of generated signals (outputs) may have a width of 4 bits, 12 bits, or 24 bits. Typically, for the sake of simplicity of both hardware and software, 4 bits of data would be stored in an 8-bit memory location, 12 bits data would be stored in a 16-bit memory location and 24 bits would be stored in a 32-bit memory location. The remaining bits at each location are unused, which wastes memory resources.
U.S. Pat. No. 5,559,969 describes a system in which one or more processors have a different data word width from other processors and from a memory device. Data words are concatenated so that the resulting data word matches the word width of the memory device. For example, four 8-bit data words may be concatenated into a 32-bit word, if the word-width of the memory device is 32 bits. Data may be re-ordered (formatted), for example to convert a big-endian data word to a little-endian data word. The system improves storage efficiency when the word width of the memory device is an integer multiple of the data word width. However, U.S. Pat. No. 5,559,969 does not disclose how to store data words in a memory device when the word width of the memory device is not an integer multiple of the data word width.
More efficient storage and retrieval of data of any bit-width in a memory having a given bit-width may prove useful, for example to allow a microprocessor to access the memory in a manner that is transparent to the microprocessor.